Binary counters, a basic circuit of digital devices, are fabricated using very large scale integrated circuit technology. Once fabricated, each binary counter must be tested to assure all components are operable. It also may be desirable for the counter to be testable once the integrated circuit, in which the counter is embedded, is incorporated in a device. Since test equipment is very expensive and the cost of test equipment, as well as its operating costs, are distributed over the product tested using the test equipment, the time required to test circuits adds to the cost of integrated circuits. It is therefore desirable to maximize the amount of testing achieved while minimizing the duration of testing.
One technique that could be used to test an n-stage binary counter is to count from 1 through 2.sup.n. Such a test requires 2.sup.n clock cycles to count through all 2.sup.n counter states. Since the duration of testing a counter would be relatively long by stepping through each counter state, with the duration of testing being even larger for larger n, alternative techniques for testing counters are desirable.
Other techniques for testing multi-stage binary counters are set forth in the text Principles of CMOS VLSI Design by N. H. Weste and K. Eshraghian, at pages 486 and 487. One such technique, illustrated in FIG. 2, reduces the length of a counter to segments of a predetermined length by having a test signal block the carry-propagate at each n/k-bit boundary. Using this technique, an n-bit counter 200 having k groups 202 each n/k-bits long can be exhaustively tested using 2.sup.n/k test vectors. The carry-propagate signal between the adjacent groups in preloadable counters can be tested with a few additional vectors when the counter can be initialized with a predetermined value, as is known in the art. Each group 202 of n/k-bits has a carry input signal 204 that is the carry output signal 206 from the next lower group 202. Each group 202 includes a multiplexer 208 that receives as inputs the carry-input signal from an adjacent group 202 and a test carry signal TST2 on bus 210. The select input 212 that controls which of the inputs to multiplexer 208 is selected as the output is coupled to bus 214 to receive test signal TST1. When test signal TST1 on bus 214 is a logic high, the carry input signal 204 is blocked and carry test signal TST2 on bus 210 is injected as the carry input signal for all groups 202 of counter 200. The n/k-bits output from each n/k-bit counter 218 are logically combined by AND gate 220. The output of AND gate 220 is high when all n/k-bits are high, and is low otherwise.
The technique disclosed in Weste employs multiplexers to block the carry-propagation between adjacent n/k-bit counters during testing. This technique has the shortcoming of requiring the carry-propagation to pass through the k-1 multiplexers during operation of the counter, that is when the counter is not being tested. Thus, the ease of testing the counter disclosed by Weste is at the expense of operational speed.
U.S. Pat. No. 5,381,453, which is hereby incorporated by reference, discloses a variation of the technique disclosed in Weste in which additional logic is incorporated into the counter to enable the counter to be tested in fewer clock cycles.
What is desired is a carry propagation technique applicable to binary counters that does not adversely impact the carry-propagation delay, while retaining the advantage of being able to block the carry propagation during testing of the counter.